In a semiconductor fabrication process, it is common to form designed patterns by etching a substrate and/or a to-be-etched layer using a patterned photoresist layer as an etching mask. The patterned photoresist layer may be formed by exposing and developing a photoresist layer.
With the continuous development of the semiconductor process, the size of semiconductor devices have been continuously shrunk; and the minimum line width of the patterned photoresist layer has also become smaller and smaller. Further, in order to match the requirements of shrinking the minimum line width of the photoresist layer, the thickness and the hardness of the photoresist layer have also been continuously reduced, thus it has become more and more difficult to control the line width roughness (LWR) of the patterned photoresist layer. In an etching process, the photoresist near to the top of an opening may become slanting because of the effect of the etching gas. That is, the right angles at the top of the photoresist patterns may become round angles. Such round angles may affect the side surface morphology of the patterns formed by a subsequent etching process.
Further, because the photoresist near to the top of the opening may become slanting; and/or may be partially removed because of the etching process, the size of the openings may be greater than the designed size, and as a result, the subsequently formed patterns in a to-be-etched layer may be greater than the designed size.
Further, when the device densities at different positions of a substrate are different, the size of the patterns formed by an etching process using the photoresist having a same pattern size as an etching mask may also be different. Therefore, the electrical properties of the semiconductor devices may be significantly affected. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.